This patent application is a continuation-in-part of U.S. patent application Ser. No. 10/935,960, filed on Sep. 8, 2004, entitled TERNARY AND MULTI-VALUE DIGITAL SCRAMBLERS, DESCRAMBLERS AND SEQUENCE GENERATORS, which is hereby incorporated herein by reference in its entirety, and which claims priority to U.S. Provisional Application No. 60/547,683, filed Feb. 25, 2004.
This invention relates to the realization of binary and multi-valued digital (non-binary) logic devices by implementing binary and multi-valued two input/single output functions. More specifically, it relates to realizing these functions by applying externally controlled conducting and non-conducting gates and binary and multi-valued inverters.
The foundation of digital binary electronics lies in the translation of binary logic into 2-valued switches. This translation can be performed in such a way that with a limited set of binary logic functions all possible binary logic functions can be realized.
It is well known that with a set of two binary switching functions (the NOT and the NAND function) all other binary functions can be realized. The NOT and NAND functions are said to form an adequate set of connectives.
All 16 binary (two inputs/single output) functions can thus be created from the NOT and the AND function. Those functions include the well known AND, OR, NAND, NOR, NOT and XOR functions.
Using the NOT and NAND function to create other logic functions is not always the most economical way to do so. For instance, implementing the exclusive or (XOR) function this way will require 3 NAND and two NOT functions. There are better, more economical ways to implement this function.
A similar theory can be applied to ternary and multi-valued logic. In multi-value logic, a logic state can assume one of x values where x is greater than or equal to 3. One can find adequate sets of ternary connectives. Unfortunately, creation of the rest of the ternary functions from the set of adequate ternary connectives may not be efficient. Another disadvantage may be that the ternary functions in the adequate set may not be easy to realize.
The approach of applying the ternary set of adequate connectives (and of any multi-valued connectives) may not be an economical or even a possible way to realize all other ternary (or multi-valued) functions. While it may be possible to find a limited set of multi-valued connectives, it may take too many of these connectives to realize desirable functions. It may also be very difficult to find physical switching mechanisms that can realize the individual connectives.
The current way of realizing binary or in general digital switching circuits is by first finding a mathematical logic expression that describes the functions that have to be realized. In general, the selected functions represent realizable logic devices. An important mathematical property of these expressions is the associative property, which affects the way how they can be grouped. This combined with the causal property (which means that an expression has to be executed before its result is available) determines largely how a logical expression is realized with logical devices. These properties become apparent in circuits such as digital ripple adders. Several approaches exist to minimize the number of logic functions and execution steps in what is generally called multi-level logic expressions. The overall speed of executing a multi-level logic expression is generally limited by its level of complexity and the related propagation delays of the individual functions.
Accordingly, there is a need for providing for and improving the implementation of ternary and multi-value functions.